On 03/30/2010 04:59 AM, Xiao Guangrong wrote:
When we cached shadow page tables, one guest page table may have many shadow pages, take below case for example: (RO+U) ---> |------| __ |------| (W+U ) ---> | GP1 | | | GP2 | (W+P ) ---> |------| |--> |------| There have 3 kinds of permission mapping to GP1, so we should allocate 3 shadow pages for GP1 and 3 shadow pages for GP2. And it has 3 class permissions(R/W, U/S, X/NX) in x86's architecture, for the worst case, we should allocate 2^3 pages for every paging mapping level. This waste is caused by that we only set the permission bits in PTE, not in the middle mapping level. So, i think we can mapping guest page table's permission into cache shadow page table, then it can be shared between many shadow page tables if their map to the same gust physics address. For above case, we only need 2 pages. Any comments?
We've considered this in the past, it makes sense. The big question is whether any guests actually map the same page table through PDEs with different permissions (mapping the same page table through multiple PDEs is very common, but always with the same permissions). Do you know of any such guest?
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