v2: Rebased on alistair23/riscv-to-apply.next
Patch #1-#5 reviewed.
Philippe Mathieu-Daudé (16):
target/riscv: Remove unuseful KVM stubs
target/riscv: Remove unused 'instmap.h' header in translate.c
target/riscv: Restrict sysemu specific header to user emulation
target/riscv: Restrict 'rv128' machine to TCG accelerator
target/riscv: Move sysemu-specific files to target/riscv/sysemu/
target/riscv: Restrict riscv_cpu_do_interrupt() to sysemu
target/riscv: Move TCG-specific files to target/riscv/tcg/
target/riscv: Move TCG-specific cpu_get_tb_cpu_state() to tcg/cpu.c
target/riscv: Expose some 'trigger' prototypes from debug.c
target/riscv: Extract TCG-specific code from debug.c
target/riscv: Move sysemu-specific debug files to target/riscv/sysemu/
target/riscv: Expose riscv_cpu_pending_to_irq() from cpu_helper.c
target/riscv: Move TCG/sysemu-specific code to tcg/sysemu/cpu_helper.c
target/riscv: Move sysemu-specific code to sysemu/cpu_helper.c
target/riscv: Restrict TCG-specific prototype declarations
gitlab-ci.d/crossbuilds: Add KVM riscv64 cross-build jobs
target/riscv/cpu.h | 27 +-
target/riscv/internals.h | 4 +
target/riscv/{ => sysemu}/debug.h | 6 +
target/riscv/{ => sysemu}/instmap.h | 0
target/riscv/{ => sysemu}/kvm_riscv.h | 0
target/riscv/{ => sysemu}/pmp.h | 0
target/riscv/{ => sysemu}/pmu.h | 0
target/riscv/{ => sysemu}/time_helper.h | 0
target/riscv/{ => tcg}/XVentanaCondOps.decode | 0
target/riscv/{ => tcg}/insn16.decode | 0
target/riscv/{ => tcg}/insn32.decode | 0
target/riscv/{ => tcg}/xthead.decode | 0
hw/riscv/virt.c | 2 +-
target/riscv/cpu.c | 33 +-
target/riscv/cpu_helper.c | 1692 +----------------
target/riscv/csr.c | 6 +-
target/riscv/{ => sysemu}/arch_dump.c | 0
target/riscv/sysemu/cpu_helper.c | 863 +++++++++
target/riscv/{ => sysemu}/debug.c | 153 +-
target/riscv/{ => sysemu}/kvm-stub.c | 0
target/riscv/{ => sysemu}/kvm.c | 4 +-
target/riscv/{ => sysemu}/machine.c | 0
target/riscv/{ => sysemu}/monitor.c | 0
target/riscv/{ => sysemu}/pmp.c | 0
target/riscv/{ => sysemu}/pmu.c | 0
target/riscv/{ => sysemu}/riscv-qmp-cmds.c | 0
target/riscv/{ => sysemu}/time_helper.c | 0
target/riscv/{ => tcg}/bitmanip_helper.c | 0
target/riscv/tcg/cpu.c | 98 +
target/riscv/{ => tcg}/crypto_helper.c | 0
target/riscv/{ => tcg}/fpu_helper.c | 0
target/riscv/{ => tcg}/m128_helper.c | 0
target/riscv/{ => tcg}/op_helper.c | 0
target/riscv/tcg/sysemu/cpu_helper.c | 765 ++++++++
target/riscv/tcg/sysemu/debug.c | 165 ++
target/riscv/tcg/tcg-stub.c | 31 +
target/riscv/{ => tcg}/translate.c | 1 -
target/riscv/{ => tcg}/vector_helper.c | 0
target/riscv/{ => tcg}/zce_helper.c | 0
.gitlab-ci.d/crossbuilds.yml | 8 +
target/riscv/meson.build | 33 +-
target/riscv/sysemu/meson.build | 13 +
target/riscv/tcg/meson.build | 22 +
target/riscv/tcg/sysemu/meson.build | 4 +
44 files changed, 2037 insertions(+), 1893 deletions(-)
rename target/riscv/{ => sysemu}/debug.h (96%)
rename target/riscv/{ => sysemu}/instmap.h (100%)
rename target/riscv/{ => sysemu}/kvm_riscv.h (100%)
rename target/riscv/{ => sysemu}/pmp.h (100%)
rename target/riscv/{ => sysemu}/pmu.h (100%)
rename target/riscv/{ => sysemu}/time_helper.h (100%)
rename target/riscv/{ => tcg}/XVentanaCondOps.decode (100%)
rename target/riscv/{ => tcg}/insn16.decode (100%)
rename target/riscv/{ => tcg}/insn32.decode (100%)
rename target/riscv/{ => tcg}/xthead.decode (100%)
rename target/riscv/{ => sysemu}/arch_dump.c (100%)
create mode 100644 target/riscv/sysemu/cpu_helper.c
rename target/riscv/{ => sysemu}/debug.c (83%)
rename target/riscv/{ => sysemu}/kvm-stub.c (100%)
rename target/riscv/{ => sysemu}/kvm.c (99%)
rename target/riscv/{ => sysemu}/machine.c (100%)
rename target/riscv/{ => sysemu}/monitor.c (100%)
rename target/riscv/{ => sysemu}/pmp.c (100%)
rename target/riscv/{ => sysemu}/pmu.c (100%)
rename target/riscv/{ => sysemu}/riscv-qmp-cmds.c (100%)
rename target/riscv/{ => sysemu}/time_helper.c (100%)
rename target/riscv/{ => tcg}/bitmanip_helper.c (100%)
create mode 100644 target/riscv/tcg/cpu.c
rename target/riscv/{ => tcg}/crypto_helper.c (100%)
rename target/riscv/{ => tcg}/fpu_helper.c (100%)
rename target/riscv/{ => tcg}/m128_helper.c (100%)
rename target/riscv/{ => tcg}/op_helper.c (100%)
create mode 100644 target/riscv/tcg/sysemu/cpu_helper.c
create mode 100644 target/riscv/tcg/sysemu/debug.c
create mode 100644 target/riscv/tcg/tcg-stub.c
rename target/riscv/{ => tcg}/translate.c (99%)
rename target/riscv/{ => tcg}/vector_helper.c (100%)
rename target/riscv/{ => tcg}/zce_helper.c (100%)
create mode 100644 target/riscv/sysemu/meson.build
create mode 100644 target/riscv/tcg/meson.build
create mode 100644 target/riscv/tcg/sysemu/meson.build
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2.38.1
