vLBR event could be inactive in two case: a. host per cpu pinned LBR event occupy LBR when vLBR event is created b. vLBR event is preempted by host per cpu pinned LBR event during vm exit handler. When vLBR event is inactive, guest couldn't access LBR msr, and it is forced into error state and is excluded from schedule by perf scheduler. So vLBR event couldn't be active through perf scheduler even if host per cpu pinned LBR event has released LBR, kvm could enable vLBR event proactively, then vLBR event may be active and LBR msr could be passthrough into guest. Signed-off-by: Xiong Zhang <xiong.y.zhang@xxxxxxxxx> --- arch/x86/kvm/vmx/pmu_intel.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 741efe2c497b..5a3ab8c8711b 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -314,7 +314,16 @@ static bool intel_pmu_handle_lbr_msrs_access(struct kvm_vcpu *vcpu, if (!intel_pmu_is_valid_lbr_msr(vcpu, index)) return false; - if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0) + /* vLBR event may be inactive, but physical LBR may be free now. + * but vLBR event is pinned event, once it is inactive state, perf + * will force it to error state in merge_sched_in() and exclude it from + * perf schedule, so even if LBR is free now, vLBR event couldn't be active + * through perf scheduler and vLBR event could be active through + * perf_event_enable(). + */ + if (lbr_desc->event && (lbr_desc->event->state == PERF_EVENT_STATE_ERROR)) + perf_event_enable(lbr_desc->event); + else if (!lbr_desc->event && intel_pmu_create_guest_lbr_event(vcpu) < 0) goto dummy; /* -- 2.25.1
