Add defines for Intel's LBR info MSRs, and a define (along with a snarky message) for AMD's lovely mispredict bit that is shoved into the LBR MSRs themselves. The AMD mispredict bit will be used to address false positives in the LBRV tests. Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx> --- lib/x86/msr.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/lib/x86/msr.h b/lib/x86/msr.h index 0e3fd037..8abccf86 100644 --- a/lib/x86/msr.h +++ b/lib/x86/msr.h @@ -81,6 +81,17 @@ #define MSR_IA32_LASTINTFROMIP 0x000001dd #define MSR_IA32_LASTINTTOIP 0x000001de +/* Yes, AMD does indeed record mispredict info in the LBR records themselves. */ +#define AMD_LBR_RECORD_MISPREDICT BIT_ULL(63) + +#define LBR_INFO_MISPRED BIT_ULL(63) +#define LBR_INFO_IN_TX BIT_ULL(62) +#define LBR_INFO_ABORT BIT_ULL(61) +#define LBR_INFO_CYC_CNT_VALID BIT_ULL(60) +#define LBR_INFO_CYCLES 0xffff +#define LBR_INFO_BR_TYPE_OFFSET 56 +#define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) + /* DEBUGCTLMSR bits (others vary by model): */ #define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ #define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */ -- 2.41.0.162.gfafddb0af9-goog
