Hi Marc, On 6/6/23 18:22, Marc Zyngier wrote: > On Tue, 06 Jun 2023 10:29:36 +0100, > Eric Auger <eauger@xxxxxxxxxx> wrote: >> >> Hi Marc, >> On 6/6/23 09:30, Marc Zyngier wrote: >>> Hey Eric, >>> >>> On Mon, 05 Jun 2023 12:28:12 +0100, >>> Eric Auger <eauger@xxxxxxxxxx> wrote: >>>> >>>> Hi Marc, >>>> >>>> On 5/15/23 19:30, Marc Zyngier wrote: >>>>> This is the 4th drop of NV support on arm64 for this year. >>>>> >>>>> For the previous episodes, see [1]. >>>>> >>>>> What's changed: >>>>> >>>>> - New framework to track system register traps that are reinjected in >>>>> guest EL2. It is expected to replace the discrete handling we have >>>>> enjoyed so far, which didn't scale at all. This has already fixed a >>>>> number of bugs that were hidden (a bunch of traps were never >>>>> forwarded...). Still a work in progress, but this is going in the >>>>> right direction. >>>>> >>>>> - Allow the L1 hypervisor to have a S2 that has an input larger than >>>>> the L0 IPA space. This fixes a number of subtle issues, depending on >>>>> how the initial guest was created. >>>>> >>>>> - Consequently, the patch series has gone longer again. Boo. But >>>>> hopefully some of it is easier to review... >>>>> >>>>> [1] https://lore.kernel.org/r/20230405154008.3552854-1-maz@xxxxxxxxxx >>>>> >>>>> Andre Przywara (1): >>>>> KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ >>>> >>>> I guess you have executed kselftests on L1 guests. Have all the tests >>>> passed there? On my end it stalls in the KVM_RUN. >>> >>> No, I hardly run any kselftest, because they are just not designed to >>> run at EL2 at all. There's some work to be done there, but I just >>> don't have the bandwidth for that (hint, wink...) >> >> oh OK, I missed that point. If nobody is working on this I can start >> looking at it. Would be interesting to run them on nested guest too. > > If you want to pick this up, it would be extremely helpful. And no, > nobody is really looking into it at the moment, so it's all yours! OK I will study that then :-) Eric > > Thanks, > > M. >
