On Tue, Jun 06, 2023 at 12:59:23PM +0800,
Yuan Yao <yuan.yao@xxxxxxxxxxxxxxx> wrote:
> On Sun, May 28, 2023 at 09:19:13PM -0700, isaku.yamahata@xxxxxxxxx wrote:
> > From: Isaku Yamahata <isaku.yamahata@xxxxxxxxx>
> >
> > The TDX support will need the "suppress #VE" bit (bit 63) set as the
> > initial value for SPTE. To reduce code change size, introduce a new macro
> > SHADOW_NONPRESENT_VALUE for the initial value for the shadow page table
> > entry (SPTE) and replace hard-coded value 0 for it. Initialize shadow page
> > tables with their value.
> >
> > The plan is to unconditionally set the "suppress #VE" bit for both AMD and
> > Intel as: 1) AMD hardware uses the bit 63 as NX for present SPTE and
> > ignored for non-present SPTE; 2) for conventional VMX guests, KVM never
> > enables the "EPT-violation #VE" in VMCS control and "suppress #VE" bit is
> > ignored by hardware.
> >
> > Signed-off-by: Sean Christopherson <sean.j.christopherson@xxxxxxxxx>
> > Signed-off-by: Isaku Yamahata <isaku.yamahata@xxxxxxxxx>
> > ---
> > arch/x86/kvm/mmu/mmu.c | 20 +++++++++++++++-----
> > arch/x86/kvm/mmu/paging_tmpl.h | 2 +-
> > arch/x86/kvm/mmu/spte.h | 2 ++
> > arch/x86/kvm/mmu/tdp_mmu.c | 14 +++++++-------
> > 4 files changed, 25 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/x86/kvm/mmu/mmu.c b/arch/x86/kvm/mmu/mmu.c
> > index dc2b9a2f717c..1b6fd4434e96 100644
> > --- a/arch/x86/kvm/mmu/mmu.c
> > +++ b/arch/x86/kvm/mmu/mmu.c
> > @@ -576,9 +576,9 @@ static u64 mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
> >
> > if (!is_shadow_present_pte(old_spte) ||
> > !spte_has_volatile_bits(old_spte))
> > - __update_clear_spte_fast(sptep, 0ull);
> > + __update_clear_spte_fast(sptep, SHADOW_NONPRESENT_VALUE);
> > else
> > - old_spte = __update_clear_spte_slow(sptep, 0ull);
> > + old_spte = __update_clear_spte_slow(sptep, SHADOW_NONPRESENT_VALUE);
> >
> > if (!is_shadow_present_pte(old_spte))
> > return old_spte;
> > @@ -612,7 +612,7 @@ static u64 mmu_spte_clear_track_bits(struct kvm *kvm, u64 *sptep)
> > */
> > static void mmu_spte_clear_no_track(u64 *sptep)
> > {
> > - __update_clear_spte_fast(sptep, 0ull);
> > + __update_clear_spte_fast(sptep, SHADOW_NONPRESENT_VALUE);
> > }
> >
> > static u64 mmu_spte_get_lockless(u64 *sptep)
> > @@ -1969,7 +1969,8 @@ static bool kvm_sync_page_check(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
> >
> > static int kvm_sync_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, int i)
> > {
> > - if (!sp->spt[i])
> > + /* sp->spt[i] has initial value of shadow page table allocation */
> > + if (sp->spt[i] != SHADOW_NONPRESENT_VALUE)
>
> This should be "sp->spt[i] == SHADOW_NONPRESENT_VALUE" ? Looks all present spt[i]
> are skipped without sync for shadow paging.
Oop, you're right. Will fix it.
Thanks,
--
Isaku Yamahata <isaku.yamahata@xxxxxxxxx>
