On Fri, 2 Jun 2023 19:50:33 -0700, Reiji Watanabe wrote:
> This series will fix bugs in KVM's handling of PMUSERENR_EL0.
>
> With PMU access support from EL0 [1], the perf subsystem would
> set CR and ER bits of PMUSERENR_EL0 as needed to allow EL0 to have
> a direct access to PMU counters. However, KVM appears to assume
> that the register value is always zero for the host EL0, and has
> the following two problems in handling the register.
>
> [...]
Applied to fixes, thanks!
[1/2] KVM: arm64: PMU: Restore the host's PMUSERENR_EL0
commit: 8681f71759010503892f9e3ddb05f65c0f21b690
[2/2] KVM: arm64: PMU: Don't overwrite PMUSERENR with vcpu loaded
commit: 0c2f9acf6ae74118385f7a7d48f4b2d93637b628
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
