From: Jinrong Liang <cloudliang@xxxxxxxxxxx>
KVM user sapce may control the Intel guest PMU version number via
CPUID.0AH:EAX[07:00]. A test is added to check if a typical PMU register
that is not available at the current version number is leaking.
Co-developed-by: Like Xu <likexu@xxxxxxxxxxx>
Signed-off-by: Like Xu <likexu@xxxxxxxxxxx>
Signed-off-by: Jinrong Liang <cloudliang@xxxxxxxxxxx>
---
.../kvm/x86_64/pmu_basic_functionality_test.c | 64 +++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
index 108cfe254095..7da3eaf9ab5a 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_basic_functionality_test.c
@@ -368,11 +368,75 @@ static void intel_test_fixed_counters(void)
}
}
+static void intel_guest_check_pmu_version(uint8_t version)
+{
+ switch (version) {
+ case 0:
+ GUEST_SYNC(wrmsr_safe(MSR_INTEL_ARCH_PMU_GPCTR, 0xffffull));
+ case 1:
+ GUEST_SYNC(wrmsr_safe(MSR_CORE_PERF_GLOBAL_CTRL, 0x1ull));
+ case 2:
+ /*
+ * AnyThread Bit is only supported in version 3
+ *
+ * The strange thing is that when version=0, writing ANY-Any
+ * Thread bit (bit 21) in MSR_P6_EVNTSEL0 and MSR_P6_EVNTSEL1
+ * will not generate #GP. While writing ANY-Any Thread bit
+ * (bit 21) in MSR_P6_EVNTSEL0+x (MAX_GP_CTR_NUM > x > 2) to
+ * ANY-Any Thread bit (bit 21) will generate #GP.
+ */
+ if (version == 0)
+ break;
+
+ GUEST_SYNC(wrmsr_safe(MSR_P6_EVNTSEL0, EVENTSEL_ANY));
+ break;
+ default:
+ /* KVM currently supports up to pmu version 2 */
+ GUEST_SYNC(GP_VECTOR);
+ }
+
+ GUEST_DONE();
+}
+
+static void test_pmu_version_setup(struct kvm_vcpu *vcpu, uint8_t version,
+ uint64_t expected)
+{
+ struct kvm_cpuid_entry2 *entry;
+ uint64_t msr_val;
+
+ entry = vcpu_get_cpuid_entry(vcpu, 0xa);
+ entry->eax = (entry->eax & ~PMU_VERSION_MASK) | version;
+ vcpu_set_cpuid(vcpu);
+
+ vcpu_args_set(vcpu, 1, version);
+ while (run_vcpu(vcpu, &msr_val) != UCALL_DONE) {
+ TEST_ASSERT(msr_val == expected,
+ "Something beyond this PMU version is leaked.");
+ }
+}
+
+static void intel_test_pmu_version(void)
+{
+ struct kvm_vm *vm;
+ struct kvm_vcpu *vcpu;
+ uint8_t version, unsupported_version = X86_INTEL_PMU_VERSION + 1;
+
+ TEST_REQUIRE(X86_INTEL_MAX_FIXED_CTR_NUM > 2);
+
+ for (version = 0; version <= unsupported_version; version++) {
+ vm = pmu_vm_create_with_one_vcpu(&vcpu,
+ intel_guest_check_pmu_version);
+ test_pmu_version_setup(vcpu, version, GP_VECTOR);
+ kvm_vm_free(vm);
+ }
+}
+
static void intel_test_pmu_cpuid(void)
{
intel_test_arch_events();
intel_test_counters_num();
intel_test_fixed_counters();
+ intel_test_pmu_version();
}
int main(int argc, char *argv[])
--
2.31.1
