AMD Zen3 and newer processors support shadow stack, a feature designed to protect against ROP (return-oriented programming) attacks in which an attacker manipulates return addresses on the call stack in order to execute arbitrary code. To prevent this, shadow stacks can be allocated that are only used by control transfer and return instructions. When a CALL instruction is issued, it writes the return address to both the program stack and the shadow stack. When the subsequent RET instruction is issued, it pops the return address from both stacks and compares them. If the addresses don't match, a control-protection exception is raised. Shadow stack and a related feature, Indirect Branch Tracking (IBT), are collectively referred to as Control-flow Enforcement Technology (CET). However, current AMD processors only support shadow stack and not IBT. This series adds support for shadow stack in SVM guests and builds upon the support added in the CET guest support patch series [1]. Additional patches are required to support shadow stack enabled guests in qemu [2] and glibc [3]. [1]: CET guest support patches https://lore.kernel.org/all/20230511040857.6094-1-weijiang.yang@xxxxxxxxx/ [2]: CET qemu patches https://patchwork.ozlabs.org/project/qemu-devel/patch/20201013051935.6052-2-weijiang.yang@xxxxxxxxx/ [3]: glibc tree containing necessary updates https://gitlab.com/x86-glibc/glibc/-/tree/users/hjl/cet/master/ --- v2: - Rebased on v3 of the Intel CET virtualization series, dropping the patch that moved cet_is_msr_accessible to common code as that has been pulled into the Intel series. - Minor change removing curly brackets around if statement introduced in patch 6/6. --- Note to maintainers: This series is split into two parts. This series pertains to KVM and should apply to the KVM tree. Another patch which I will be submitting separately entitled, "[RFC PATCH v2] x86/sev-es: Include XSS value in GHCB CPUID request", pertains to the guest kernel and should apply to the tip tree. However, I realized that both series depend on the following line from patch 5/6 in this series: diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h index e7c7379d6ac7..8f91376273e0 100644 --- a/arch/x86/include/asm/svm.h +++ b/arch/x86/include/asm/svm.h @@ -677,5 +677,6 @@ DEFINE_GHCB_ACCESSORS(sw_exit_info_1) DEFINE_GHCB_ACCESSORS(sw_exit_info_2) DEFINE_GHCB_ACCESSORS(sw_scratch) DEFINE_GHCB_ACCESSORS(xcr0) +DEFINE_GHCB_ACCESSORS(xss) #endif Please advise on how to resolve this situation. Thanks, John John Allen (6): KVM: x86: SVM: Emulate reads and writes to shadow stack MSRs KVM: x86: SVM: Update dump_vmcb with shadow stack save area additions KVM: x86: SVM: Pass through shadow stack MSRs KVM: SVM: Save shadow stack host state on VMRUN KVM: SVM: Add MSR_IA32_XSS to the GHCB for hypervisor kernel KVM: SVM: Add CET features to supported_xss arch/x86/include/asm/svm.h | 1 + arch/x86/kvm/svm/sev.c | 25 +++++++++++- arch/x86/kvm/svm/svm.c | 84 ++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/svm/svm.h | 2 +- 4 files changed, 109 insertions(+), 3 deletions(-) -- 2.39.1
