Hey Marc,
On Mon, May 15, 2023 at 06:00:16PM +0100, Marc Zyngier wrote:
> CTR_EL0 can often be used in userspace, and it would be nice if
> KVM didn't have to emulate it unnecessarily.
>
> While it isn't possible to trap the cache configuration registers
> indemendently from CTR_EL0 in the base ARMv8.0 architecture, FEAT_EVT
> allows these cache configuration registers (CCSIDR_EL1, CCSIDR2_EL1,
> CLIDR_EL1 and CSSELR_EL1) to be trapped indepdently by setting
> HCR_EL2.TID4.
>
> Switch to using TID4 instead of TID2 in the cases where FEAT_EVT
> is available *and* that KVM doesn't need to sanitise CTR_EL0 to
> paper over mismatched cache configurations.
>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
Just squashed the following nitpicks into your patch (trailing
whitespace, feature name).
diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/kvm_emulate.h
index a08291051ac9..35bffdec0214 100644
--- a/arch/arm64/include/asm/kvm_emulate.h
+++ b/arch/arm64/include/asm/kvm_emulate.h
@@ -100,7 +100,7 @@ static inline void vcpu_reset_hcr(struct kvm_vcpu *vcpu)
vcpu->arch.hcr_el2 |= HCR_TID4;
else
vcpu->arch.hcr_el2 |= HCR_TID2;
-
+
if (vcpu_el1_is_32bit(vcpu))
vcpu->arch.hcr_el2 &= ~HCR_RW;
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index c51870d4d492..4a2ab3f366de 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2642,7 +2642,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
},
{
- .desc = "Extended Virtualization Traps",
+ .desc = "Enhanced Virtualization Traps",
.capability = ARM64_HAS_EVT,
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
.sys_reg = SYS_ID_AA64MMFR2_EL1,
--
Thanks,
Oliver
