On Tue, 09 May 2023 03:30:16 PDT (-0700), andy.chiu@xxxxxxxxxx wrote:
From: Greentime Hu <greentime.hu@xxxxxxxxxx>
These are small and likely to be frequently called so implement as
inline routines (vs. function call).
Co-developed-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx>
Co-developed-by: Vincent Chen <vincent.chen@xxxxxxxxxx>
Signed-off-by: Vincent Chen <vincent.chen@xxxxxxxxxx>
Signed-off-by: Greentime Hu <greentime.hu@xxxxxxxxxx>
Signed-off-by: Vineet Gupta <vineetg@xxxxxxxxxxxx>
Signed-off-by: Andy Chiu <andy.chiu@xxxxxxxxxx>
Reviewed-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Reviewed-by: Heiko Stuebner <heiko.stuebner@xxxxxxxx>
Tested-by: Heiko Stuebner <heiko.stuebner@xxxxxxxx>
---
arch/riscv/include/asm/vector.h | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h
index 427a3b51df72..dfe5a321b2b4 100644
--- a/arch/riscv/include/asm/vector.h
+++ b/arch/riscv/include/asm/vector.h
@@ -11,12 +11,23 @@
#ifdef CONFIG_RISCV_ISA_V
#include <asm/hwcap.h>
+#include <asm/csr.h>
static __always_inline bool has_vector(void)
{
return riscv_has_extension_likely(RISCV_ISA_EXT_v);
}
+static __always_inline void riscv_v_enable(void)
+{
+ csr_set(CSR_SSTATUS, SR_VS);
+}
+
+static __always_inline void riscv_v_disable(void)
+{
+ csr_clear(CSR_SSTATUS, SR_VS);
+}
+
#else /* ! CONFIG_RISCV_ISA_V */
static __always_inline bool has_vector(void) { return false; }
Reviewed-by: Palmer Dabbelt <palmer@xxxxxxxxxxxx>
