From: Eric Auger <eric.auger@xxxxxxxxxx> Despite the spec does not seem to mention this, on some implementations, when the STE configuration switches from an S1+S2 cfg to an S1 only one, a C_BAD_STE error would happen if dst[3] (S2TTB) is not reset. Explicitly reset those two higher 64b fields, to prevent that. Note that this is not a bug at this moment, since a 2-stage translation setup is not yet enabled, until the following patches add its support. Reported-by: Shameer Kolothum <shameerali.kolothum.thodi@xxxxxxxxxx> Link: https://patchwork.kernel.org/cover/11449895/#23244457 Signed-off-by: Eric Auger <eric.auger@xxxxxxxxxx> Signed-off-by: Nicolin Chen <nicolinc@xxxxxxxxxx> --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index c57c70132c0b..792e8a788e2e 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1373,6 +1373,17 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid, dst[3] = cpu_to_le64(s2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); val |= FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_S2_TRANS); + } else { + /* + * Unset dst[2] and dst[3] to clear stage-2 configurations. This was observed + * on a HiSilicon implementation where, if the SMMUv3 is configured with both + * stage-1 and stage-2 mode once, it is not possible to configure it back for + * stage-1 mode for the same device (stream id). The SMMUv3 implementation on + * these boards expects to set the S2TTB field in STE to zero when using S1, + * otherwise it reports C_BAD_STE error. + */ + dst[2] = 0; + dst[3] = 0; } if (master->ats_enabled) -- 2.40.1
