Re: [PATCH v3 09/19] tcg: Add andcs and rotrs tcg gvec ops

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On 4/28/23 15:47, Lawrence Hunter wrote:
From: Nazar Kazakov <nazar.kazakov@xxxxxxxxxxxxxxx>

This commit adds helper functions and tcg operation definitions for the andcs and rotrs instructions

Signed-off-by: Nazar Kazakov <nazar.kazakov@xxxxxxxxxxxxxxx>
---
  accel/tcg/tcg-runtime-gvec.c | 11 +++++++++++
  accel/tcg/tcg-runtime.h      |  1 +
  include/tcg/tcg-op-gvec.h    |  4 ++++
  tcg/tcg-op-gvec.c            | 23 +++++++++++++++++++++++
  4 files changed, 39 insertions(+)

Queued to tcg-next as two patches, and with alterations:

+void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
+{
+    static GVecGen2s g = {
+        .fni8 = tcg_gen_andc_i64,
+        .fniv = tcg_gen_andc_vec,
+        .fno = gen_helper_gvec_andcs,
+        .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+        .vece = MO_64
+    };
+
+    tcg_gen_dup_i64(vece, c, c);
+    tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g);
+}

This needed a temporary.

+void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs,
+                        TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
+{
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    tcg_gen_sub_i32(tmp, tcg_constant_i32(1 << (vece + 3)), shift);
+    tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz);
+}

This needed the rotation count to be masked (32 - 0 == 32 is illegal).
Simplified as (-shift & mask).


r~




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