> From: Jason Gunthorpe <jgg@xxxxxxxxxx> > Sent: Tuesday, April 25, 2023 11:58 PM > > On Tue, Apr 25, 2023 at 03:48:11PM +0100, Robin Murphy wrote: > > On 2023-04-21 18:58, Jason Gunthorpe wrote: > > > On Fri, Apr 21, 2023 at 06:22:37PM +0100, Robin Murphy wrote: > > > > > > > I think a slightly more considered and slightly less wrong version of that > > > > idea is to mark it as IOMMU_RESV_MSI, and special-case direct- > mapping those > > > > on Arm (I believe it would technically be benign to do on x86 too, but > might > > > > annoy people with its pointlessness). However... > > > > > > I'd rather have a IOMMU_RESV_MSI_DIRECT and put the ARM special > case > > > in ARM code.. > > > > Maybe, but it's still actually broken either way, because how do you get > > that type into the VM? Firmware can't encode that a particular RMR > > represents the special magic hack for IOMMUFD, so now the SMMU driver > needs > > to somehow be aware when it's running in a VM offering nested > translation > > and do some more magic to inject the appropriate region, and it's all > > just... no. > > Er, I figured ARM had sorted this out somehow :( > > Eric, do you know anything about this? Where did you setup the 1:1 map > in the VM in your series? > Out of curiosity. Does this flag have different meaning on s1 vs. s2? for s1 it means 1:1 mapping. for s2 it has same meaning as IOMMU_RESV_SW_MSI stands?
