On 11/4/23 22:57, Alexey Kardashevskiy wrote:
This is to use another AMD SEV-ES hardware assisted register swap,
more detail in 5/6. In the process it's been suggested to fix other
things, here is the attempt, with the great help of amders.
The previous conversation is here:
https://lore.kernel.org/r/20230203051459.1354589-1-aik@xxxxxxx
This is based on sha1
f91f9332d782 Ingo Molnar "Merge branch into tip/master: 'x86/tdx'".
Please comment. Thanks.
Ping?
Or should I relax until the end of the nearest merge window (May
6th-ish)? :) Thanks,
Alexey Kardashevskiy (6):
KVM: SEV: move set_dr_intercepts/clr_dr_intercepts from the header
KVM: SEV: Move SEV's GP_VECTOR intercept setup to SEV
KVM: SEV-ES: explicitly disable debug
KVM: SVM/SEV/SEV-ES: Rework intercepts
KVM: SEV: Enable data breakpoints in SEV-ES
x86/sev: Do not handle #VC for DR7 read/write
arch/x86/include/asm/cpufeatures.h | 1 +
arch/x86/include/asm/svm.h | 1 +
arch/x86/kvm/svm/svm.h | 42 ---------------
arch/x86/boot/compressed/sev.c | 2 +-
arch/x86/kernel/sev.c | 6 +++
arch/x86/kvm/svm/sev.c | 54 +++++++++++++++++++-
arch/x86/kvm/svm/svm.c | 48 +++++++++++++++--
7 files changed, 105 insertions(+), 49 deletions(-)
--
Alexey
