On Wed, Feb 15, 2023, Mathias Krause wrote:
> +static void test_reg_noncanonical(void)
> +{
> + extern char nc_rsp_start, nc_rsp_end, nc_rbp_start, nc_rbp_end;
> + extern char nc_rax_start, nc_rax_end;
> + handler old_ss, old_gp;
> +
> + old_ss = handle_exception(SS_VECTOR, advance_rip_and_note_exception);
> + old_gp = handle_exception(GP_VECTOR, advance_rip_and_note_exception);
> +
> + /* RAX based, should #GP(0) */
> + exceptions = 0;
> + rip_advance = &nc_rax_end - &nc_rax_start;
> + asm volatile("nc_rax_start: orq $0, (%[msb]); nc_rax_end:\n\t"
Can't we use ASM_TRY() + exception_vector() + exception_error_code()? Installing
a dedicated handler is (slowly) being phased out. Even better, if you're willing
to take a dependency and/or wait a few weeks for my series to land[*], you should
be able to use asm_safe() to streamline this even further.
[*] https://lkml.kernel.org/r/20230406025117.738014-1-seanjc%40google.com
> + : : [msb]"a"(1ul << 63));
Use BIT_ULL(). Actually, scratch that, we have a NONCANONICAL macro. It _probably_
won't matter, but who know what will happen with things like LAM and LASS.
And why hardcode use of RAX? Won't any "r" constraint work?
E.g. I believe this can be something like:
asm_safe_report_ex(GP_VECTOR, "orq $0, (%[noncanonical]), "r" (NONCANONICAL));
report(!exception_error_code());
Or we could even add asm_safe_report_ex_ec(), e.g.
asm_safe_report_ex_ec(GP_VECTOR, 0,
"orq $0, (%[noncanonical]), "r" (NONCANONICAL));
