Add the detection code for the FEAT_NV2 feature.
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
---
arch/arm64/include/asm/kvm_nested.h | 6 ++++++
arch/arm64/kernel/cpufeature.c | 11 +++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm64/include/asm/kvm_nested.h b/arch/arm64/include/asm/kvm_nested.h
index 784168dcb0fe..a58c3df12379 100644
--- a/arch/arm64/include/asm/kvm_nested.h
+++ b/arch/arm64/include/asm/kvm_nested.h
@@ -14,6 +14,12 @@ static inline bool vcpu_has_nv(const struct kvm_vcpu *vcpu)
test_bit(KVM_ARM_VCPU_HAS_EL2, vcpu->arch.features));
}
+static inline bool vcpu_has_nv2(const struct kvm_vcpu *vcpu)
+{
+ return cpus_have_final_cap(ARM64_HAS_ENHANCED_NESTED_VIRT) &&
+ vcpu_has_nv(vcpu);
+}
+
/* Translation helpers from non-VHE EL2 to EL1 */
static inline u64 tcr_el2_ps_to_tcr_el1_ips(u64 tcr_el2)
{
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index c331c49a7d19..db877f1d3a7b 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2298,6 +2298,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.field_width = 4,
.min_field_value = ID_AA64MMFR2_EL1_NV_IMP,
},
+ {
+ .desc = "Enhanced Nested Virtualization Support",
+ .capability = ARM64_HAS_ENHANCED_NESTED_VIRT,
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .matches = has_nested_virt_support,
+ .sys_reg = SYS_ID_AA64MMFR2_EL1,
+ .sign = FTR_UNSIGNED,
+ .field_pos = ID_AA64MMFR2_EL1_NV_SHIFT,
+ .field_width = 4,
+ .min_field_value = ID_AA64MMFR2_EL1_NV_NV2,
+ },
{
.capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE,
.type = ARM64_CPUCAP_SYSTEM_FEATURE,
--
2.34.1
