+ Mark, as we just discussed this. On Wed, 29 Mar 2023 01:21:34 +0100, Reiji Watanabe <reijiw@xxxxxxxxxx> wrote: > > This series will fix bugs in KVM's handling of PMUSERENR_EL0. > > With PMU access support from EL0 [1], the perf subsystem would > set CR and ER bits of PMUSERENR_EL0 as needed to allow EL0 to have > a direct access to PMU counters. However, KVM appears to assume > that the register value is always zero for the host EL0, and has > the following two problems in handling the register. > > [A] The host EL0 might lose the direct access to PMU counters, as > KVM always clears PMUSERENR_EL0 before returning to userspace. > > [B] With VHE, the guest EL0 access to PMU counters might be trapped > to EL1 instead of to EL2 (even when PMUSERENR_EL0 for the guest > indicates that the guest EL0 has an access to the counters). > This is because, with VHE, KVM sets ER, CR, SW and EN bits of > PMUSERENR_EL0 to 1 on vcpu_load() to ensure to trap PMU access > from the guset EL0 to EL2, but those bits might be cleared by > the perf subsystem after vcpu_load() (when PMU counters are > programmed for the vPMU emulation). > > Patch-1 will fix [A], and Patch-2 will fix [B] respectively. > The series is based on v6.3-rc4. > > [1] https://github.com/torvalds/linux/commit/83a7a4d643d33a8b74a42229346b7ed7139fcef9 > > Reiji Watanabe (2): > KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 > KVM: arm64: PMU: Ensure to trap PMU access from EL0 to EL2 > > arch/arm64/include/asm/kvm_host.h | 3 +++ > arch/arm64/kvm/hyp/include/hyp/switch.h | 28 +++++++++++++------------ > 2 files changed, 18 insertions(+), 13 deletions(-) > > > base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa > -- > 2.40.0.348.gf938b09366-goog > > -- Without deviation from the norm, progress is not possible.
