It recently became apparent that the way we switch our EL1&0 translation regime is not entirely fool proof. On taking an exception from EL1&0 to EL2(&0), the page table walker is allowed to carry on with speculative walks started from EL1&0 while running at EL2 (see R_LFHQG). Given that the PTW may be actively using the EL1&0 system registers, the only safe way to deal with it is to issue a DSB before changing any of it. We already did the right thing for SPE and TRBE, but ignored the PTW for unknown reasons (probably because the architecture wasn't crystal clear at the time). This requires a bit of surgery in the nvhe code, though most of these patches are comments so that my future self can understand the purpose of these barriers. The VHE code is largely unaffected, thanks to the DSB in the context switch. Marc Zyngier (2): KVM: arm64: nvhe: Synchronise with page table walker on MMU update KVM: arm64: vhe: Synchronise with page table walker on MMU update arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 -- arch/arm64/kvm/hyp/nvhe/mem_protect.c | 7 +++++++ arch/arm64/kvm/hyp/nvhe/switch.c | 18 ++++++++++++++++++ arch/arm64/kvm/hyp/nvhe/tlb.c | 7 +++++++ arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 12 ++++++++++++ 5 files changed, 44 insertions(+), 2 deletions(-) -- 2.34.1
