[kvm-unit-tests PATCH 3/3] x86/msr: Add testcases for MSR_IA32_FLUSH_CMD and its L1D_FLUSH command

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Add test coverage to verify MSR_IA32_FLUSH_CMD is write-only, that it can
be written with '0' (nop command) and '1' (L1D flush command) when the L1D
flush command is suported, and that writing any other bit (1-63) triggers
a #GP due to the bits/commands being reserved.

Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
---
 lib/x86/msr.h       |  3 +++
 lib/x86/processor.h |  1 +
 x86/msr.c           | 11 +++++++++++
 3 files changed, 15 insertions(+)

diff --git a/lib/x86/msr.h b/lib/x86/msr.h
index 29fff553..0e3fd037 100644
--- a/lib/x86/msr.h
+++ b/lib/x86/msr.h
@@ -36,6 +36,9 @@
 #define MSR_IA32_PRED_CMD               0x00000049
 #define PRED_CMD_IBPB			BIT(0)
 
+#define MSR_IA32_FLUSH_CMD		0x0000010b
+#define L1D_FLUSH			BIT(0)
+
 #define MSR_IA32_PMC0                  0x000004c1
 #define MSR_IA32_PERFCTR0		0x000000c1
 #define MSR_IA32_PERFCTR1		0x000000c2
diff --git a/lib/x86/processor.h b/lib/x86/processor.h
index aed6d180..e32c84f7 100644
--- a/lib/x86/processor.h
+++ b/lib/x86/processor.h
@@ -246,6 +246,7 @@ static inline bool is_intel(void)
 #define	X86_FEATURE_SHSTK		(CPUID(0x7, 0, ECX, 7))
 #define	X86_FEATURE_IBT			(CPUID(0x7, 0, EDX, 20))
 #define	X86_FEATURE_SPEC_CTRL		(CPUID(0x7, 0, EDX, 26))
+#define	X86_FEATURE_FLUSH_L1D		(CPUID(0x7, 0, EDX, 28))
 #define	X86_FEATURE_ARCH_CAPABILITIES	(CPUID(0x7, 0, EDX, 29))
 #define	X86_FEATURE_PKS			(CPUID(0x7, 0, ECX, 31))
 
diff --git a/x86/msr.c b/x86/msr.c
index 13cb6391..f6be2be7 100644
--- a/x86/msr.c
+++ b/x86/msr.c
@@ -295,6 +295,17 @@ static void test_cmd_msrs(void)
 	}
 	for (i = 1; i < 64; i++)
 		test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", BIT_ULL(i));
+
+	test_rdmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD");
+	if (this_cpu_has(X86_FEATURE_FLUSH_L1D)) {
+		test_wrmsr(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", 0);
+		test_wrmsr(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", L1D_FLUSH);
+	} else {
+		test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", 0);
+		test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", L1D_FLUSH);
+	}
+	for (i = 1; i < 64; i++)
+		test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", BIT_ULL(i));
 }
 
 int main(int ac, char **av)
-- 
2.40.0.348.gf938b09366-goog




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