On Wed, Mar 22, 2023, Pawan Gupta wrote:
> On Tue, Mar 21, 2023 at 06:14:39PM -0700, Sean Christopherson wrote:
> > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> > index 85bb535fc321..b32edaf5a74b 100644
> > --- a/arch/x86/kvm/svm/svm.c
> > +++ b/arch/x86/kvm/svm/svm.c
> > @@ -95,6 +95,7 @@ static const struct svm_direct_access_msrs {
> > #endif
> > { .index = MSR_IA32_SPEC_CTRL, .always = false },
> > { .index = MSR_IA32_PRED_CMD, .always = false },
> > + { .index = MSR_IA32_FLUSH_CMD, .always = false },
> > { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
> > { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
> > { .index = MSR_IA32_LASTINTFROMIP, .always = false },
> > @@ -4140,6 +4141,10 @@ static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
> > set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0,
> > !!guest_has_pred_cmd_msr(vcpu));
> >
> > + if (boot_cpu_has(X86_FEATURE_FLUSH_L1D))
>
> Just curious, will this ever be true on AMD hardware? AFAIK,
> X86_FEATURE_FLUSH_L1D is Intel-defined CPU feature.
Don't know myself, but I assume/home there was actual motivation behind adding
support for AMD.
