Intel Linear-address masking (LAM) [1], modifies the checking that is applied to *64-bit* linear addresses, allowing software to use of the untranslated address bits for metadata. The patch series add test cases for LAM: Patch 1 makes change to HOST_CR3 tests in vmx. If LAM is supported, VM entry allows CR3.LAM_U48 (bit 62) and CR3.LAM_U57 (bit 61) to be set in CR3 field. Change the test result expectations when setting CR3.LAM_U48 or CR3.LAM_U57 on vmlaunch tests when LAM is supported. Patch 2~4 add test cases for LAM supervisor mode and user mode, including: - For supervisor mode CR4.LAM_SUP toggle Memory/MMIO access with tagged pointer INVLPG INVPCID INVVPID (also used to cover VMX instruction vmexit path) - For user mode CR3 LAM bits toggle Memory/MMIO access with tagged pointer [1] Intel ISE https://cdrdv2.intel.com/v1/dl/getContent/671368 Chapter Linear Address Masking (LAM) --- Changelog v1 --> v2: Add cases to test INVLPG, INVPCID, INVVPID with LAM_SUP Add cases to test LAM_{U48,U57} Binbin Wu (3): x86: Allow setting of CR3 LAM bits if LAM supported x86: Add test cases for LAM_{U48,U57} x86: Add test case for INVVPID with LAM Robert Hoo (1): x86: Add test case for LAM_SUP lib/x86/processor.h | 7 + x86/Makefile.x86_64 | 1 + x86/lam.c | 340 ++++++++++++++++++++++++++++++++++++++++++++ x86/unittests.cfg | 10 ++ x86/vmx_tests.c | 79 +++++++++- 5 files changed, 436 insertions(+), 1 deletion(-) create mode 100644 x86/lam.c base-commit: e3c5c3ef2524c58023073c0fadde2e8ae3c04ec6 -- 2.25.1
