Instructions on s390 must be halfword aligned.
Add two tests for that.
These currently fail when using TCG.
v3 -> v2:
* pick up R-b (thanks Janosch)
* use br instead of bcr (thanks Claudio)
* use text section instead of rodata for ex target (thanks Claudio)
* fix label position (thanks Claudio)
v1 -> v2:
* rebase
* use PSW macros
* simplify odd psw test (thanks Claudio)
* rename some identifiers
* pick up R-b (thanks Claudio)
Nina Schoetterl-Glausch (3):
s390x/spec_ex: Use PSW macro
s390x/spec_ex: Add test introducing odd address into PSW
s390x/spec_ex: Add test of EXECUTE with odd target address
s390x/spec_ex.c | 85 +++++++++++++++++++++++++++++++++++++++++++------
1 file changed, 76 insertions(+), 9 deletions(-)
Range-diff against v2:
1: d82f4fb6 ! 1: 6ae1eb7d s390x/spec_ex: Use PSW macro
@@ Commit message
Replace explicit psw definition by PSW macro.
No functional change intended.
+ Reviewed-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
Signed-off-by: Nina Schoetterl-Glausch <nsg@xxxxxxxxxxxxx>
## s390x/spec_ex.c ##
2: e537797f ! 2: a0d02438 s390x/spec_ex: Add test introducing odd address into PSW
@@ s390x/spec_ex.c: static int psw_bit_12_is_1(void)
+" . = . + 1\n"
+"misaligned_code:\n"
+" larl %r0,0\n"
-+" bcr 0xf,%r1\n"
++" br %r1\n"
+);
+
+static int psw_odd_address(void)
3: dc552880 ! 3: e771deeb s390x/spec_ex: Add test of EXECUTE with odd target address
@@ s390x/spec_ex.c: static int short_psw_bit_12_is_0(void)
+ uint64_t pre_target_addr;
+ int to = 0, from = 0x0dd;
+
-+ asm volatile ( ".pushsection .rodata\n"
-+ "pre_odd_ex_target:\n"
++ asm volatile ( ".pushsection .text.ex_odd\n"
+ " .balign 2\n"
++ "pre_odd_ex_target:\n"
+ " . = . + 1\n"
+ " lr %[to],%[from]\n"
+ " .popsection\n"
base-commit: e3c5c3ef2524c58023073c0fadde2e8ae3c04ec6
--
2.39.1
