Add testing for the event "Instructions retired" (0xc0) in the PMU
event filter on both Intel and AMD to ensure that the event doesn't
count when it is disallowed. Unlike most of the other events, the
event "Instructions retired", will be incremented by KVM when an
instruction is emulated. Test that this case is being properly handled
and that KVM doesn't increment the counter when that event is
disallowed.
Signed-off-by: Aaron Lewis <aaronlewis@xxxxxxxxxx>
---
.../kvm/x86_64/pmu_event_filter_test.c | 80 ++++++++++++++-----
1 file changed, 62 insertions(+), 18 deletions(-)
diff --git a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c
index 78bb48fcd33e..9e932b99d4fa 100644
--- a/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c
+++ b/tools/testing/selftests/kvm/x86_64/pmu_event_filter_test.c
@@ -54,6 +54,21 @@
#define AMD_ZEN_BR_RETIRED EVENT(0xc2, 0)
+
+/*
+ * "Retired instructions", from Processor Programming Reference
+ * (PPR) for AMD Family 17h Model 01h, Revision B1 Processors,
+ * Preliminary Processor Programming Reference (PPR) for AMD Family
+ * 17h Model 31h, Revision B0 Processors, and Preliminary Processor
+ * Programming Reference (PPR) for AMD Family 19h Model 01h, Revision
+ * B1 Processors Volume 1 of 2.
+ * --- and ---
+ * "Instructions retired", from the Intel SDM, volume 3,
+ * "Pre-defined Architectural Performance Events."
+ */
+
+#define INST_RETIRED EVENT(0xc0, 0)
+
/*
* This event list comprises Intel's eight architectural events plus
* AMD's "retired branch instructions" for Zen[123] (and possibly
@@ -61,7 +76,7 @@
*/
static const uint64_t event_list[] = {
EVENT(0x3c, 0),
- EVENT(0xc0, 0),
+ INST_RETIRED,
EVENT(0x3c, 1),
EVENT(0x2e, 0x4f),
EVENT(0x2e, 0x41),
@@ -71,6 +86,16 @@ static const uint64_t event_list[] = {
AMD_ZEN_BR_RETIRED,
};
+struct perf_results {
+ union {
+ uint64_t raw;
+ struct {
+ uint64_t br_count:32;
+ uint64_t ir_count:32;
+ };
+ };
+};
+
/*
* If we encounter a #GP during the guest PMU sanity check, then the guest
* PMU is not functional. Inform the hypervisor via GUEST_SYNC(0).
@@ -102,13 +127,20 @@ static void check_msr(uint32_t msr, uint64_t bits_to_flip)
static uint64_t test_guest(uint32_t msr_base)
{
+ struct perf_results r;
uint64_t br0, br1;
+ uint64_t ir0, ir1;
br0 = rdmsr(msr_base + 0);
+ ir0 = rdmsr(msr_base + 1);
__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
br1 = rdmsr(msr_base + 0);
+ ir1 = rdmsr(msr_base + 1);
- return br1 - br0;
+ r.br_count = br1 - br0;
+ r.ir_count = ir1 - ir0;
+
+ return r.raw;
}
static void intel_guest_code(void)
@@ -119,15 +151,17 @@ static void intel_guest_code(void)
GUEST_SYNC(1);
for (;;) {
- uint64_t count;
+ uint64_t counts;
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
wrmsr(MSR_P6_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |
ARCH_PERFMON_EVENTSEL_OS | INTEL_BR_RETIRED);
- wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0x1);
+ wrmsr(MSR_P6_EVNTSEL1, ARCH_PERFMON_EVENTSEL_ENABLE |
+ ARCH_PERFMON_EVENTSEL_OS | INST_RETIRED);
+ wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0x3);
- count = test_guest(MSR_IA32_PMC0);
- GUEST_SYNC(count);
+ counts = test_guest(MSR_IA32_PMC0);
+ GUEST_SYNC(counts);
}
}
@@ -143,14 +177,16 @@ static void amd_guest_code(void)
GUEST_SYNC(1);
for (;;) {
- uint64_t count;
+ uint64_t counts;
wrmsr(MSR_K7_EVNTSEL0, 0);
wrmsr(MSR_K7_EVNTSEL0, ARCH_PERFMON_EVENTSEL_ENABLE |
ARCH_PERFMON_EVENTSEL_OS | AMD_ZEN_BR_RETIRED);
+ wrmsr(MSR_K7_EVNTSEL1, ARCH_PERFMON_EVENTSEL_ENABLE |
+ ARCH_PERFMON_EVENTSEL_OS | INST_RETIRED);
- count = test_guest(MSR_K7_PERFCTR0);
- GUEST_SYNC(count);
+ counts = test_guest(MSR_K7_PERFCTR0);
+ GUEST_SYNC(counts);
}
}
@@ -250,19 +286,25 @@ static struct kvm_pmu_event_filter *remove_event(struct kvm_pmu_event_filter *f,
return f;
}
-#define ASSERT_PMC_COUNTING(count) \
+#define ASSERT_PMC_COUNTING(counts) \
do { \
- if (count && count != NUM_BRANCHES) \
- pr_info("%s: Branch instructions retired = %lu (expected %u)\n", \
- __func__, count, NUM_BRANCHES); \
- TEST_ASSERT(count, "%s: Branch instructions retired = %lu (expected > 0)", \
- __func__, count); \
+ struct perf_results r = {.raw = counts}; \
+ if (r.br_count && r.br_count != NUM_BRANCHES) \
+ pr_info("%s: Branch instructions retired = %u (expected %u)\n", \
+ __func__, r.br_count, NUM_BRANCHES); \
+ TEST_ASSERT(r.br_count, "%s: Branch instructions retired = %u (expected > 0)", \
+ __func__, r.br_count); \
+ TEST_ASSERT(r.ir_count, "%s: Instructions retired = %u (expected > 0)", \
+ __func__, r.ir_count); \
} while (0)
-#define ASSERT_PMC_NOT_COUNTING(count) \
+#define ASSERT_PMC_NOT_COUNTING(counts) \
do { \
- TEST_ASSERT(!count, "%s: Branch instructions retired = %lu (expected 0)", \
- __func__, count); \
+ struct perf_results r = {.raw = counts}; \
+ TEST_ASSERT(!r.br_count, "%s: Branch instructions retired = %u (expected 0)", \
+ __func__, r.br_count); \
+ TEST_ASSERT(!r.ir_count, "%s: Instructions retired = %u (expected 0)", \
+ __func__, r.ir_count); \
} while (0)
static void test_without_filter(struct kvm_vcpu *vcpu)
@@ -317,6 +359,7 @@ static void test_not_member_deny_list(struct kvm_vcpu *vcpu)
struct kvm_pmu_event_filter *f = event_filter(KVM_PMU_EVENT_DENY);
uint64_t c;
+ remove_event(f, INST_RETIRED);
remove_event(f, INTEL_BR_RETIRED);
remove_event(f, AMD_ZEN_BR_RETIRED);
c = test_with_filter(vcpu, f);
@@ -330,6 +373,7 @@ static void test_not_member_allow_list(struct kvm_vcpu *vcpu)
struct kvm_pmu_event_filter *f = event_filter(KVM_PMU_EVENT_ALLOW);
uint64_t c;
+ remove_event(f, INST_RETIRED);
remove_event(f, INTEL_BR_RETIRED);
remove_event(f, AMD_ZEN_BR_RETIRED);
c = test_with_filter(vcpu, f);
--
2.40.0.rc0.216.gc4246ad0f0-goog
