On 02/26/2010 04:42 PM, Peter Zijlstra wrote:
Also, intel debugstore things requires a host linear address,
It requires a linear address, not a host linear address. Of course, it
might not like the linear address mappings changing under its feet. If
it has a private tlb, then this won't work.
again, not
something a vcpu can easily provide (although that might be worked
around with an msr trap, but that still limits you to 1 page data sizes,
not a limitation all software will respect).
If you're willing to pin pages, you can map the guest's buffer. That
won't work if BTS can happen in parallel with a #VMEXIT, or if there are
interactions with npt/ept. Will have to ask the vendors.
All that said, what we really want is for Intel+AMD to come up with
proper hw PMU virtualization support that makes it easy to rotate the
full PMU in and out for a guest. Then this whole discussion will become
a non issue.
As it stands there simply are a number of PMU features that defy being
virtualized, simply because the virt stuff doesn't do system topology.
So even if they were to support a virtualized pmu, it would likely be a
different beast than the native hardware is, and it will be several
hardware models in the future, coming up with a paravirt interface and
getting !linux hosts to adapt and !linux guests to use is probably as
'easy'.
!linux hosts are someone else's problem, but how would be get !linux
guests to use a soft pmu?
The only way I see that happening is if a soft pmu is standardized
across hypervisors, which is unfortunately unlikely.
--
error compiling committee.c: too many arguments to function
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