> From: Jason Gunthorpe <jgg@xxxxxxxxxx> > Sent: Monday, February 13, 2023 10:46 PM > > On Mon, Feb 13, 2023 at 02:24:40AM +0000, Tian, Kevin wrote: > > > > This is because the cache tag and the io page table top are in > > > different 64 bit words so atomic writes don't cover both, and thus the > > > IOMMU HW could tear the two stores and mismatch the cache tag to the > > > table top. This would corrupt the cache. > > > > VT-d spec recommends using 128bit cmpxchg instruction to update > > page table pointer and DID together. > > Oh really? Such a thing exists? That neat! > yes. see cmpxchg_double().
