Hi Andy,
On 1/25/23 06:20, Andy Chiu wrote:
+static bool insn_is_vector(u32 insn_buf)
+{
+ u32 opcode = insn_buf & __INSN_OPCODE_MASK;
+ /*
+ * All V-related instructions, including CSR operations are 4-Byte. So,
+ * do not handle if the instruction length is not 4-Byte.
+ */
+ if (unlikely(GET_INSN_LENGTH(insn_buf) != 4))
+ return false;
+ if (opcode == OPCODE_VECTOR) {
+ return true;
+ } else if (opcode == OPCODE_LOADFP || opcode == OPCODE_STOREFP) {
+ u32 width = EXTRACT_LOAD_STORE_FP_WIDTH(insn_buf);
+
+ if (width == LSFP_WIDTH_RVV_8 || width == LSFP_WIDTH_RVV_16 ||
+ width == LSFP_WIDTH_RVV_32 || width == LSFP_WIDTH_RVV_64)
+ return true;
What is the purpose of checking FP opcodes here ?
+ } else if (opcode == RVG_OPCODE_SYSTEM) {
+ u32 csr = EXTRACT_SYSTEM_CSR(insn_buf);
+
+ if ((csr >= CSR_VSTART && csr <= CSR_VCSR) ||
+ (csr >= CSR_VL && csr <= CSR_VLENB))
+ return true;
+ }
+ return false;
+}
