On Wed, Feb 01, 2023 at 03:12:39PM -0800, Atish Patra wrote:
> This patch fixes/improve few minor things in SBI PMU extension
> definition.
>
> 1. Align all the firmware event names.
> 2. Add macros for bit positions in cache event ID & ops.
>
> The changes were small enough to combine them together instead
> of creating 1 liner patches.
>
> Signed-off-by: Atish Patra <atishp@xxxxxxxxxxxx>
> ---
> arch/riscv/include/asm/sbi.h | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 4ca7fba..945b7be 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -169,9 +169,9 @@ enum sbi_pmu_fw_generic_events_t {
> SBI_PMU_FW_ILLEGAL_INSN = 4,
> SBI_PMU_FW_SET_TIMER = 5,
> SBI_PMU_FW_IPI_SENT = 6,
> - SBI_PMU_FW_IPI_RECVD = 7,
> + SBI_PMU_FW_IPI_RCVD = 7,
> SBI_PMU_FW_FENCE_I_SENT = 8,
> - SBI_PMU_FW_FENCE_I_RECVD = 9,
> + SBI_PMU_FW_FENCE_I_RCVD = 9,
> SBI_PMU_FW_SFENCE_VMA_SENT = 10,
> SBI_PMU_FW_SFENCE_VMA_RCVD = 11,
> SBI_PMU_FW_SFENCE_VMA_ASID_SENT = 12,
> @@ -215,6 +215,9 @@ enum sbi_pmu_ctr_type {
> #define SBI_PMU_EVENT_CACHE_OP_ID_CODE_MASK 0x06
> #define SBI_PMU_EVENT_CACHE_RESULT_ID_CODE_MASK 0x01
>
> +#define SBI_PMU_EVENT_CACHE_ID_SHIFT 3
> +#define SBI_PMU_EVENT_CACHE_OP_SHIFT 1
> +
> #define SBI_PMU_EVENT_IDX_INVALID 0xFFFFFFFF
>
> /* Flags defined for config matching function */
> --
> 2.25.1
>
Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
