Signed-off-by: Lawrence Hunter <lawrence.hunter@xxxxxxxxxxxxxxx>
---
target/riscv/helper.h | 1 +
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 +
target/riscv/vcrypto_helper.c | 12 ++++++++++++
4 files changed, 15 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index a155272701..32f1179e29 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1141,3 +1141,4 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl)
DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e26ea1df08..b4d88dd1cb 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -895,3 +895,4 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm
vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm
vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm
+vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm
diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc
index 19ce4c7431..533141e559 100644
--- a/target/riscv/insn_trans/trans_rvzvkb.c.inc
+++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc
@@ -94,3 +94,4 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a)
}
GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check)
+GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check)
diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c
index 022b941131..46e2e510c5 100644
--- a/target/riscv/vcrypto_helper.c
+++ b/target/riscv/vcrypto_helper.c
@@ -42,6 +42,18 @@ static void do_vclmulh_vv(void *vd, void *vs1, void *vs2, int i)
((uint64_t *)vd)[i] = (result >> 64);
}
+static void do_vclmulh_vx(void *vd, target_long rs1, void *vs2, int i)
+{
+ __uint128_t result = 0;
+ for (int j = 63; j >= 0; j--) {
+ if ((rs1 >> j) & 1) {
+ result ^= (((__uint128_t)(((uint64_t *)vs2)[i])) << j);
+ }
+ }
+ ((uint64_t *)vd)[i] = (result >> 64);
+}
+
GEN_VEXT_VV(vclmul_vv, 8)
GEN_VEXT_VX(vclmul_vx, 8)
GEN_VEXT_VV(vclmulh_vv, 8)
+GEN_VEXT_VX(vclmulh_vx, 8)
--
2.39.1
