On Sat, Jan 28, 2023 at 02:52:23PM +0100, Joerg Roedel wrote: > Yeah, something like this will be the fix. I am still thinking about > the right place to put the volatile to make it explicit to the situation > we are encountering here (which is SEV-ES specific). > > Best would be an explicit barrier in C code between sev_es_ist_enter() > and the DR7 read, but all barriers I tried to far only seem to affect > memory instructions and had no influence on the DR7 read (which is > obviously not considered as a memory read by the compiler). > > The best place to put the barrier is in the sev_es_ist_enter() inline > function, right after the static_call to __sev_es_ist_enter(). Okay, after some investigation I was not able to find a compiler barrier which affects DR7 read ordering. This leaves us with the only solution of directly forbidding DR7 register access re-ordering by adding a volatile to the asm, like you did before. I will send a fix later today. Regards, Joerg
