These are small and likely to be frequently called so implement as inline routines (vs. function call). Co-developed-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> Co-developed-by: Vincent Chen <vincent.chen@xxxxxxxxxx> Signed-off-by: Vincent Chen <vincent.chen@xxxxxxxxxx> Signed-off-by: Greentime Hu <greentime.hu@xxxxxxxxxx> Signed-off-by: Vineet Gupta <vineetg@xxxxxxxxxxxx> [vineetg: create new patch from meshup, introduced asm variant] Signed-off-by: Andy Chiu <andy.chiu@xxxxxxxxxx> [andy.chiu: remove calls from asm thus remove asm vaiant] --- arch/riscv/include/asm/vector.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/vector.h b/arch/riscv/include/asm/vector.h index 917c8867e702..0fda0faf5277 100644 --- a/arch/riscv/include/asm/vector.h +++ b/arch/riscv/include/asm/vector.h @@ -11,12 +11,23 @@ #ifdef CONFIG_RISCV_ISA_V #include <asm/hwcap.h> +#include <asm/csr.h> static __always_inline bool has_vector(void) { return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_VECTOR]); } +static __always_inline void rvv_enable(void) +{ + csr_set(CSR_SSTATUS, SR_VS); +} + +static __always_inline void rvv_disable(void) +{ + csr_clear(CSR_SSTATUS, SR_VS); +} + #else /* ! CONFIG_RISCV_ISA_V */ static __always_inline bool has_vector(void) { return false; } -- 2.17.1