> > > Intel folks, > > Do you happen to know exactly what scenario prompted adding the freeze+unfreeze > code? Is there something I'm forgetting/missing, or is it possible we can go > with a simpler implementation? It's documented in the "TDX TDP MMU design doc" patch: +TDX concurrent populating +------------------------- ...... + +Without freezing the entry, the following race can happen. Suppose two vcpus +are faulting on the same GPA and the 2M and 4K level entries aren't populated +yet. + +* vcpu 1: update 2M level EPT entry +* vcpu 2: update 4K level EPT entry +* vcpu 2: TDX SEAMCALL to update 4K secure EPT entry => error +* vcpu 1: TDX SEAMCALL to update 2M secure EPT entry + ( I guess such material will be more useful in the comment. And perhaps we can get rid of the "TDX TDP MMU design doc" patch in this series at least for now as probably nobody will look at it :-) )
