Hi Marc,
On Fri, Jan 20, 2023 at 6:11 AM Marc Zyngier <maz@xxxxxxxxxx> wrote:
>
> On Fri, 20 Jan 2023 14:04:12 +0000,
> Marc Zyngier <maz@xxxxxxxxxx> wrote:
> >
> > On Tue, 17 Jan 2023 01:35:35 +0000,
> > Reiji Watanabe <reijiw@xxxxxxxxxx> wrote:
> > >
> > > On vCPU reset, PMCNTEN{SET,CLR}_EL0, PMINTEN{SET,CLR}_EL1, and
> > > PMOVS{SET,CLR}_EL1 for a vCPU are reset by reset_pmu_reg().
> > > This function clears RAZ bits of those registers corresponding
> > > to unimplemented event counters on the vCPU, and sets bits
> > > corresponding to implemented event counters to a predefined
> > > pseudo UNKNOWN value (some bits are set to 1).
> > >
> > > The function identifies (un)implemented event counters on the
> > > vCPU based on the PMCR_EL1.N value on the host. Using the host
> > > value for this would be problematic when KVM supports letting
> > > userspace set PMCR_EL1.N to a value different from the host value
> > > (some of the RAZ bits of those registers could end up being set to 1).
> > >
> > > Fix reset_pmu_reg() to clear the registers so that it can ensure
> > > that all the RAZ bits are cleared even when the PMCR_EL1.N value
> > > for the vCPU is different from the host value.
> > >
> > > Signed-off-by: Reiji Watanabe <reijiw@xxxxxxxxxx>
> > > ---
> > > arch/arm64/kvm/sys_regs.c | 10 +---------
> > > 1 file changed, 1 insertion(+), 9 deletions(-)
> > >
> > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > > index c6cbfe6b854b..ec4bdaf71a15 100644
> > > --- a/arch/arm64/kvm/sys_regs.c
> > > +++ b/arch/arm64/kvm/sys_regs.c
> > > @@ -604,19 +604,11 @@ static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
> > >
> > > static void reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
> > > {
> > > - u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
> > > -
> > > /* No PMU available, any PMU reg may UNDEF... */
> > > if (!kvm_arm_support_pmu_v3())
> > > return;
> >
> > Is this still true? We remove the PMCR_EL0 access just below.
> >
> > >
> > > - n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
> > > - n &= ARMV8_PMU_PMCR_N_MASK;
> > > - if (n)
> > > - mask |= GENMASK(n - 1, 0);
> > > -
> > > - reset_unknown(vcpu, r);
> > > - __vcpu_sys_reg(vcpu, r->reg) &= mask;
> > > + __vcpu_sys_reg(vcpu, r->reg) = 0;
> > > }
> >
> > At the end of the day, this function has no dependency on the host at
> > all, and only writes 0 to the per-vcpu register.
> >
> > So why not get rid of it altogether and have:
> >
> > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> > index c6cbfe6b854b..1d1514b89d75 100644
> > --- a/arch/arm64/kvm/sys_regs.c
> > +++ b/arch/arm64/kvm/sys_regs.c
> > @@ -976,7 +976,7 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> > trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
> >
> > #define PMU_SYS_REG(r) \
> > - SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility
> > + SYS_DESC(r), .visibility = pmu_visibility
> >
> > /* Macro to expand the PMEVCNTRn_EL0 register */
> > #define PMU_PMEVCNTR_EL0(n) \
> >
> > which would fall-back the specified reset value (zero by default)?
>
> Scratch that, we need:
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index c6cbfe6b854b..6f6a928c92ec 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -976,7 +976,7 @@ static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
> trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
>
> #define PMU_SYS_REG(r) \
> - SYS_DESC(r), .reset = reset_pmu_reg, .visibility = pmu_visibility
> + SYS_DESC(r), .reset = reset_val, .visibility = pmu_visibility
>
> /* Macro to expand the PMEVCNTRn_EL0 register */
> #define PMU_PMEVCNTR_EL0(n) \
>
> But otherwise, this should be enough.
Yes, that's true. I will fix that in v3.
Thank you!
Reiji
