On 1/16/23 10:13, Borislav Petkov wrote: >> /* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ >> #define X86_FEATURE_NO_NESTED_DATA_BP (20*32+ 0) /* "" AMD No Nested Data Breakpoints */ >> +#define X86_FEATURE_LFENCE_RDTSC (20*32+ 2) /* "" LFENCE always serializing / synchronizes RDTSC */ > Hmm, a synthetic bit which gets replaced with a vendor one and then the other > vendors set it too. I don't see why that cannot work but we probably should be > careful here. > > dhansen, am I missing an angle? I don't think so. I'd be surprised if we don't have a _few_ other cases like this around, but nothing is coming to mind. Either way, it doesn't seem problematic.
