On Fri, Jan 6, 2023 at 5:10 PM Sean Christopherson <seanjc@xxxxxxxxxx> wrote:
>
> Don't clear the "read" bits for x2APIC registers above SELF_IPI (APIC regs
Odd use of quotation marks in the shortlog and here.
> 0x400 - 0xff0, MSRs 0x840 - 0x8ff). KVM doesn't emulate registers in that
> space (there are a smattering of AMD-only extensions) and so should
> intercept reads in order to inject #GP. When APICv is fully enabled,
> Intel hardware doesn't validate the registers on RDMSR and instead blindly
> retrieves data from the vAPIC page, i.e. it's software's responsibility to
> intercept reads to non-existent MSRs.
>
> Fixes: 8d14695f9542 ("x86, apicv: add virtual x2apic support")
> Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
Reviewed-by: Jim Mattson <jmattson@xxxxxxxxxx>
