On Sat, 2023-01-07 at 01:10 +0000, Sean Christopherson wrote:
> Reject attempts to set bits 63:32 for 32-bit x2APIC registers, i.e. all
> x2APIC registers except ICR. Per Intel's SDM:
>
> Non-zero writes (by WRMSR instruction) to reserved bits to these
> registers will raise a general protection fault exception
>
> Opportunistically fix a typo in a nearby comment.
>
> Reported-by: Marc Orr <marcorr@xxxxxxxxxx>
> Cc: stable@xxxxxxxxxxxxxxx
> Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
> ---
> arch/x86/kvm/lapic.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index f77da92c6ea6..bf53e4752f30 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -3108,13 +3108,17 @@ static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data)
> static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data)
> {
> /*
> - * ICR is a 64-bit register in x2APIC mode (and Hyper'v PV vAPIC) and
> + * ICR is a 64-bit register in x2APIC mode (and Hyper-V PV vAPIC) and
> * can be written as such, all other registers remain accessible only
> * through 32-bit reads/writes.
> */
> if (reg == APIC_ICR)
> return kvm_x2apic_icr_write(apic, data);
>
> + /* Bits 63:32 are reserved in all other registers. */
> + if (data >> 32)
> + return 1;
> +
> return kvm_lapic_reg_write(apic, reg, (u32)data);
> }
>
Reviewed-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx>
Best regards,
Maxim Levitsky
