[PATCH v2 0/5] target/i386: Update AMD EPYC CPU Models

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This series adds following changes.
a. Allow versioned CPUs to specify new cache_info pointers.
b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the
   cache_info.complex_indexing.
c. Introduce EPYC-Milan-v2 by adding few missing feature bits.
---
v2:
  Refreshed the patches on top of latest master.
  Changed the feature NULL_SELECT_CLEARS_BASE to NULL_SEL_CLR_BASE to
  match the kernel name.
  https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phillips@xxxxxxx/

v1: https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/


Babu Moger (3):
  target/i386: Add a couple of feature bits in 8000_0008_EBX
  target/i386: Add feature bits for CPUID_Fn80000021_EAX
  target/i386: Add missing feature bits in EPYC-Milan model

Michael Roth (2):
  target/i386: allow versioned CPUs to specify new cache_info
  target/i386: Add new EPYC CPU versions with updated cache_info

 target/i386/cpu.c | 252 +++++++++++++++++++++++++++++++++++++++++++++-
 target/i386/cpu.h |  12 +++
 2 files changed, 259 insertions(+), 5 deletions(-)

-- 
2.34.1




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