* Jes Sorensen <Jes.Sorensen@xxxxxxxxxx> wrote: > > Agree about favouring modern processors. > > You certainly cannot emulate the Core2 on a P4. The Core2 is Perfmon v2, > whereas Nehalem and Atom are v3 if I remember correctly. [...] Of course you can emulate a good portion of it, as long as there's perf support on the host side for P4. If the guest programs a cachemiss event, you program a cachemiss perf event on the host and feed its values to the emulated MSR state. You _dont_ program the raw PMU on the host side - just use the API i outlined to get struct perf_event. The emulation wont be perfect: not all events will count and not all events will be available in a P4 (and some Core2 events might not even make sense in a P4), but that is reality as well: often documented events dont count, and often non-documented events count. What matters to 99.9% of people who actually use this stuff is a few core sets of events - which are available in P4s and in Core2 as well. Cycles, instructions, branches, maybe cache-misses. Sometimes FPU stuff. For Linux<->Linux the sanest, tier-1 approach would be to map sys_perf_open() on the guest side over to the host, transparently, via a paravirt driver. Ingo -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
