Re: [PATCH v3 5/9] KVM: x86: MMU: Integrate LAM bits when build guest CR3

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On Wed, 2022-12-21 at 15:50 +0800, Yu Zhang wrote:
> > No. CR4.LAM_SUP isn't an enablement switch over CR3.LAM_U{48,57},
> > they're parallel relationship, CR4.LAM_SUP controls supervisor mode
> > addresses has LAM or not while CR3.LAM_U controls user mode
> > address's
> > LAM enablement.
> 
> Unfortunately, the spec(the one in your cover letter) has a bug in
> "10.1 ENUMERATION, ENABLING, AND CONFIGURATION":
> 
> CR4.LAM_SUP enables and configures LAM for supervisor pointers:
> • If CR3.LAM_SUP = 0, LAM is not enabled for supervisor pointers.
> • If CR3.LAM_SUP = 1, LAM is enabled for supervisor pointers with a
> width determined by the paging mode:
> 
> Based on the context, I think "CR3.LAM_SUP" should be "CR4.LAM_SUP".
> 
> I believe it could just be a typo. 

Ah, right, I hold the same belief with you. We can report it to ISE
author;-)

> But it is confusing enough.
> 
> B.R.
> Yu




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