On Tue, Nov 15, 2022, Xiaoyao Li wrote:
> On 11/10/2022 9:52 AM, Jiaxi Chen wrote:
> > cpuid_leaf[12] CPUID_7_1_EAX has only two bits are in use currently:
> >
> > - AVX-VNNI CPUID.(EAX=7,ECX=1):EAX[bit 4]
> > - AVX512-BF16 CPUID.(EAX=7,ECX=1):EAX[bit 5]
> >
> > These two bits have no other kernel usages other than the guest
> > CPUID advertisement in KVM. Given that and to save space for kernel
> > feature bits, move these two bits to the kvm-only subleaves. The
> > existing leaf cpuid_leafs[12] is set to CPUID_LNX_5 so future feature
> > can pick it. This basically reverts:
> >
> > - commit b85a0425d805 ("Enumerate AVX Vector Neural Network
> > instructions")
> > - commit b302e4b176d0 ("x86/cpufeatures: Enumerate the new AVX512
> > BFLOAT16 instructions")
> > - commit 1085a6b585d7 ("KVM: Expose AVX_VNNI instruction to guset")
>
> FYI, LAM support has been queued in tip https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?id=aa387b1b1e666cacffc0b7ac7e0949a68013b2d9
>
> It adds
>
> +#define X86_FEATURE_LAM (12*32+26) /* Linear Address Masking */
>
> and conflict with this patch.
>
> Seen from the ISE, there are more bits defined in CPUID_7_1_EAX. And I
> believe Intel will define more and it's likely some of them will be used by
> kernel just like LAM.
Heh, are any of the bits you believe Intel will add publicly documented? :-)
LAM could be scattered, but if more bits are expected that's probably a waste of
time and effort.
Thanks for the heads up!
