Add a new capability to detect "Stage-2 Translation table
break-before-make" (FEAT_BBM) level 2.
Signed-off-by: Ricardo Koller <ricarkol@xxxxxxxxxx>
---
arch/arm64/kernel/cpufeature.c | 11 +++++++++++
arch/arm64/tools/cpucaps | 1 +
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 6062454a9067..ff97fb05d430 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2339,6 +2339,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
.min_field_value = 1,
.matches = has_cpuid_feature,
},
+ {
+ .desc = "Stage-2 Translation table break-before-make level 2",
+ .type = ARM64_CPUCAP_SYSTEM_FEATURE,
+ .capability = ARM64_HAS_STAGE2_BBM2,
+ .sys_reg = SYS_ID_AA64MMFR2_EL1,
+ .sign = FTR_UNSIGNED,
+ .field_pos = ID_AA64MMFR2_EL1_BBM_SHIFT,
+ .field_width = 4,
+ .min_field_value = 2,
+ .matches = has_cpuid_feature,
+ },
{
.desc = "TLB range maintenance instructions",
.capability = ARM64_HAS_TLB_RANGE,
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index f1c0347ec31a..f421adbdb08b 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -36,6 +36,7 @@ HAS_PAN
HAS_RAS_EXTN
HAS_RNG
HAS_SB
+HAS_STAGE2_BBM2
HAS_STAGE2_FWB
HAS_SYSREG_GIC_CPUIF
HAS_TIDCP1
--
2.38.1.431.g37b22c650d-goog
