On Mon, Nov 07, 2022, Oliver Upton wrote: > Use RCU to safely walk the stage-2 page tables in parallel. Acquire and > release the RCU read lock when traversing the page tables. Defer the > freeing of table memory to an RCU callback. Indirect the calls into RCU > and provide stubs for hypervisor code, as RCU is not available in such a > context. > > The RCU protection doesn't amount to much at the moment, as readers are > already protected by the read-write lock (all walkers that free table > memory take the write lock). Nonetheless, a subsequent change will > futher relax the locking requirements around the stage-2 MMU, thereby > depending on RCU. Two somewhat off-topic questions (because I'm curious): 1. Are there plans to enable "fast" page faults on ARM? E.g. to fixup access faults (handle_access_fault()) and/or write-protection faults without acquiring mmu_lock? 2. If the answer to (1) is "yes!", what's the plan to protect the lockless walks for the RCU-less hypervisor code?