On 11/4/22 22:36, Kim Phillips wrote:
@@ -730,6 +730,8 @@ void kvm_set_cpu_caps(void)
0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) |
F(SME_COHERENT));
+ kvm_cpu_cap_mask(CPUID_8000_0021_EAX, F(AUTOIBRS));
This should also include bits 0, 2 and 6. Feel free to add #defines for
them in cpuid.c if x86 maintainers do not want them in cpufeatures.h.
There should also be something like:
if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
kvm_cpu_cap_set(CPUID_8000_0021_EAX, F(AMD_LFENCE_RDTSC));
if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
kvm_cpu_cap_set(CPUID_8000_0021_EAX, F(NSCB);
so that...
@@ -1211,12 +1213,13 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
* EAX 0 NNDBP, Processor ignores nested data breakpoints
* EAX 2 LAS, LFENCE always serializing
* EAX 6 NSCB, Null selector clear base
+ * EAX 8 Automatic IBRS
*
* Other defined bits are for MSRs that KVM does not expose:
* EAX 3 SPCL, SMM page configuration lock
* EAX 13 PCMSR, Prefetch control MSR
*/
- entry->eax &= BIT(0) | BIT(2) | BIT(6);
+ entry->eax &= BIT(0) | BIT(2) | BIT(6) | BIT(8);
if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC))
entry->eax |= BIT(2);
if (!static_cpu_has_bug(X86_BUG_NULL_SEG))
entry->eax |= BIT(6);
... these five lines become simply
cpuid_entry_override(entry, CPUID_8000_0021_EAX);
In the end these should be two patches:
- kvm, x86: use CPU capabilities for CPUID[0x80000021].EAX
- kvm, x86: support AMD automatic IBRS
Thanks,
Paolo
