On Mon, Sep 19, 2022, Like Xu wrote: > From: Like Xu <likexu@xxxxxxxxxxx> > > The AMD PerfMonV2 defines three registers similar to part of the > Intel v2 PMU registers, including the GLOBAL_CTRL, GLOBAL_STATUS > and GLOBAL_OVF_CTRL MSRs. For better code reuse, this specific > part of the handling can be extracted to make it generic for X86. > > The new non-prefix pmc_is_enabled() works well as legacy AMD vPMU > version is indexeqd as 1. Note that the specific *_is_valid_msr will > continue to be used to avoid cross-vendor msr access. Please state what the patch is doing and why. The above provides a small part of the "why", and alludes to the "what", but never actually states what is being done.
