From: Like Xu <likexu@xxxxxxxxxxx>
On virtual platforms without PDCM support (e.g. AMD), #GP
failure on MSR_IA32_PERF_CAPABILITIES is completely avoidable.
Suggested-by: Sean Christopherson <seanjc@xxxxxxxxxx>
Signed-off-by: Like Xu <likexu@xxxxxxxxxxx>
---
lib/x86/processor.h | 8 ++++++++
x86/pmu.c | 2 +-
x86/pmu_lbr.c | 2 +-
3 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/lib/x86/processor.h b/lib/x86/processor.h
index 0324220..f85abe3 100644
--- a/lib/x86/processor.h
+++ b/lib/x86/processor.h
@@ -847,4 +847,12 @@ static inline bool pmu_gp_counter_is_available(int i)
return !(cpuid(10).b & BIT(i));
}
+static inline u64 this_cpu_perf_capabilities(void)
+{
+ if (!this_cpu_has(X86_FEATURE_PDCM))
+ return 0;
+
+ return rdmsr(MSR_IA32_PERF_CAPABILITIES);
+}
+
#endif
diff --git a/x86/pmu.c b/x86/pmu.c
index d59baf1..d278bb5 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
@@ -660,7 +660,7 @@ int main(int ac, char **av)
check_counters();
- if (rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) {
+ if (this_cpu_perf_capabilities() & PMU_CAP_FW_WRITES) {
gp_counter_base = MSR_IA32_PMC0;
report_prefix_push("full-width writes");
check_counters();
diff --git a/x86/pmu_lbr.c b/x86/pmu_lbr.c
index 8dad1f1..c040b14 100644
--- a/x86/pmu_lbr.c
+++ b/x86/pmu_lbr.c
@@ -72,7 +72,7 @@ int main(int ac, char **av)
return report_summary();
}
- perf_cap = rdmsr(MSR_IA32_PERF_CAPABILITIES);
+ perf_cap = this_cpu_perf_capabilities();
if (!(perf_cap & PMU_CAP_LBR_FMT)) {
report_skip("(Architectural) LBR is not supported.");
--
2.38.1
