On Mon, Sep 19, 2022, Like Xu wrote:
> From: Like Xu <likexu@xxxxxxxxxxx>
>
> The Intel April 2022 SDM - Table 2-2. IA-32 Architectural MSRs adds
> a new architectural IA32_OVERCLOCKING_STATUS msr (0x195), plus the
> presence of IA32_CORE_CAPABILITIES (0xCF), the theoretical effective
> maximum value of the Intel GP PMCs is 14 (0xCF - 0xC1) instead of 18.
>
> But the conclusion of this speculation "14" is very fragile and can
> easily be overturned once Intel declares another meaningful arch msr
s/msr/MSR for consistency
> in the above reserved range, and even worse, just conjecture, Intel
> probably put PMCs 8-15 in a completely different range of MSR indices.
>
> A conservative proposal would be to stop at the maximum number of Intel
> GP PMCs supported today. Also subsequent changes would limit both AMD
> and Intel on the number of GP counter supported by KVM.
>
> There are some boxes like Intel P4 (non Architectural PMU) may indeed
> have 18 counters , but those counters are in a completely different msr
unnecessary whitespace before the comma. And s/msr/MSR again.
> address range and is not supported by KVM.
>
> Cc: Vitaly Kuznetsov <vkuznets@xxxxxxxxxx>
> Fixes: cf05a67b68b8 ("KVM: x86: omit "impossible" pmu MSRs from MSR list")
Does this need Cc: stable@xxxxxxxxxxxxxxx? Or is this benign enough that we don't
care?
No need for a v4, the above nits can be handled when applying.
> Suggested-by: Jim Mattson <jmattson@xxxxxxxxxx>
> Signed-off-by: Like Xu <likexu@xxxxxxxxxxx>
> Reviewed-by: Jim Mattson <jmattson@xxxxxxxxxx>
> ---
In the future, please provide a cover letter even for trivial series, it helps
(me at least) mentally organize patches.
Thanks!
