From: Like Xu <likexu@xxxxxxxxxxx> Virtualization support for SPR PEBS has officially available in the Intel SDM (June 2022) and has been validated on late stepping machines: Compared to Ice Lake Server, the PDIR counter available (Fixed 0) on SPR is unchanged, but the capability is enhanced to Instruction-Accurate PDIR (PDIR++), where PEBS is taken on the next instruction after the one that caused the overflow. Also, it introduces a new Precise Distribution (PDist) facility that eliminates the skid when a precise event is programmed on general programmable counter 0. For guest usage, KVM will require the max precise level in both cases mentioned above (other conditions may apply later), requesting the correct hardware counter (PRIR++ or PDist) from host perf as usual. Signed-off-by: Like Xu <likexu@xxxxxxxxxxx> --- Previous: https://lore.kernel.org/kvm/20220921064827.936-1-likexu@xxxxxxxxxxx/ V1 -> V2 Changelog: - move the check into a function; (Kan) arch/x86/kvm/pmu.c | 25 ++++++++++++++++++++++--- arch/x86/kvm/vmx/capabilities.h | 4 +++- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 02f9e4f245bd..5e9b0b3ea42d 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -28,9 +28,18 @@ struct x86_pmu_capability __read_mostly kvm_pmu_cap; EXPORT_SYMBOL_GPL(kvm_pmu_cap); -static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { +/* Precise Distribution of Instructions Retired (PDIR) */ +static const struct x86_cpu_id vmx_pebs_pdir_cpu[] = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL), + /* Instruction-Accurate PDIR (PDIR++) */ + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), + {} +}; + +/* Precise Distribution (PDist) */ +static const struct x86_cpu_id vmx_pebs_pdist_cpu[] = { + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), {} }; @@ -140,6 +149,16 @@ static void kvm_perf_overflow(struct perf_event *perf_event, __kvm_perf_overflow(pmc, true); } +static bool need_max_precise(struct kvm_pmc *pmc) +{ + if (pmc->idx == 0 && x86_match_cpu(vmx_pebs_pdist_cpu)) + return true; + if (pmc->idx == 32 && x86_match_cpu(vmx_pebs_pdir_cpu)) + return true; + + return false; +} + static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, u64 config, bool exclude_user, bool exclude_kernel, bool intr) @@ -181,11 +200,11 @@ static void pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, * the accuracy of the PEBS profiling result, because the "event IP" * in the PEBS record is calibrated on the guest side. * - * On Icelake everything is fine. Other hardware (GLC+, TNT+) that + * On Icelake everything is fine. Other hardware (TNT+) that * could possibly care here is unsupported and needs changes. */ attr.precise_ip = 1; - if (x86_match_cpu(vmx_icl_pebs_cpu) && pmc->idx == 32) + if (need_max_precise(pmc)) attr.precise_ip = 3; } diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index c5e5dfef69c7..4dc4bbe18821 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -398,7 +398,9 @@ static inline bool vmx_pt_mode_is_host_guest(void) static inline bool vmx_pebs_supported(void) { - return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept; + return boot_cpu_has(X86_FEATURE_PEBS) && + !boot_cpu_has(X86_FEATURE_HYBRID_CPU) && + kvm_pmu_cap.pebs_ept; } static inline u64 vmx_get_perf_capabilities(void) -- 2.37.3
