On Wed, May 25, 2022 at 10:40 AM Venkatesh Srinivas
<venkateshs@xxxxxxxxxxxx> wrote:
>
> From: Marc Orr <marcorr@xxxxxxxxxx>
>
> From: Venkatesh Srinivas <venkateshs@xxxxxxxxxxxx>
>
> The upper bytes of the x2APIC APIC_SELF_IPI register are reserved.
> Inject a #GP into the guest if any of these reserved bits are set.
>
> Signed-off-by: Marc Orr <marcorr@xxxxxxxxxx>
> Signed-off-by: Venkatesh Srinivas <venkateshs@xxxxxxxxxxxx>
> ---
> arch/x86/kvm/lapic.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 21ab69db689b..6f8522e8c492 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -2169,10 +2169,16 @@ static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
> break;
>
> case APIC_SELF_IPI:
> - if (apic_x2apic_mode(apic))
> - kvm_apic_send_ipi(apic, APIC_DEST_SELF | (val & APIC_VECTOR_MASK), 0);
> - else
> + /*
> + * Self-IPI exists only when x2APIC is enabled. Bits 7:0 hold
> + * the vector, everything else is reserved.
> + */
> + if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK)) {
> ret = 1;
> + break;
> + }
> + kvm_lapic_reg_write(apic, APIC_ICR,
> + APIC_DEST_SELF | (val & APIC_VECTOR_MASK));
Masking off the high bytes of 'val' is redundant here.
> break;
> default:
> ret = 1;
> --
> 2.36.1.124.g0e6072fb45-goog
>
