This patch adds a devicetree binding documentation for CDX bus. CDX bus controller dynamically detects CDX bus and the devices on these bus using CDX firmware. Signed-off-by: Nipun Gupta <nipun.gupta@xxxxxxx> --- .../devicetree/bindings/bus/xlnx,cdx.yaml | 75 +++++++++++++++++++ MAINTAINERS | 6 ++ 2 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/bus/xlnx,cdx.yaml diff --git a/Documentation/devicetree/bindings/bus/xlnx,cdx.yaml b/Documentation/devicetree/bindings/bus/xlnx,cdx.yaml new file mode 100644 index 000000000000..0aa5599ada8e --- /dev/null +++ b/Documentation/devicetree/bindings/bus/xlnx,cdx.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bus/xlnx,cdx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD CDX bus controller + +description: | + CDX bus controller for AMD devices is implemented to dynamically + detect CDX bus and devices on these bus using the firmware. + The CDX bus manages multiple FPGA based hardware devices, which + can support network, crypto or any other specialized type of + devices. These FPGA based devices can be added/modified dynamically + on run-time. + + All devices on the CDX bus will have a unique streamid (for IOMMU) + and a unique device ID (for MSI) corresponding to a requestor ID + (one to one associated with the device). The streamid and deviceid + are used to configure SMMU and GIC-ITS respectively. + + iommu-map property is used to define the set of stream ids + corresponding to each device and the associated IOMMU. + + The MSI writes are accompanied by sideband data (Device ID). + The msi-map property is used to associate the devices with the + device ID as well as the associated ITS controller. + +maintainers: + - Nipun Gupta <nipun.gupta@xxxxxxx> + - Nikhil Agarwal <nikhil.agarwal@xxxxxxx> + +properties: + compatible: + const: xlnx,cdxbus-controller-1.0 + + reg: + maxItems: 1 + + iommu-map: true + + msi-map: true + +required: + - compatible + - reg + - iommu-map + - msi-map + +additionalProperties: false + +examples: + - | + smmu@ec000000 { + compatible = "arm,smmu-v3"; + #iommu-cells = <1>; + }; + + gic@e2000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + its: gic-its@e2040000 { + compatible = "arm,gic-v3-its"; + msi-controller; + }; + }; + + cdx: cdx@4000000 { + compatible = "xlnx,cdxbus-controller-1.0"; + reg = <0x00000000 0x04000000 0 0x1000>; + /* define map for RIDs 250-259 */ + iommu-map = <250 &smmu 250 10>; + /* define msi map for RIDs 250-259 */ + msi-map = <250 &its 250 10>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 9d7f64dc0efe..f0598b3d731c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -934,6 +934,12 @@ S: Supported F: drivers/crypto/ccp/ F: include/linux/ccp.h +AMD CDX BUS DRIVER +M: Nipun Gupta <nipun.gupta@xxxxxxx> +M: Nikhil Agarwal <nikhil.agarwal@xxxxxxx> +S: Maintained +F: Documentation/devicetree/bindings/bus/xlnx,cdx.yaml + AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER - SEV SUPPORT M: Brijesh Singh <brijesh.singh@xxxxxxx> M: Tom Lendacky <thomas.lendacky@xxxxxxx> -- 2.25.1
