On 6/9/2022 3:15 pm, Sandipan Das wrote:
Hi Like,
On 8/19/2022 4:39 PM, Like Xu wrote:
From: Like Xu <likexu@xxxxxxxxxxx>
For most unit tests, the basic framework and use cases which test
any PMU counter do not require any changes, except for two things:
- No access to registers introduced only in PMU version 2 and above;
- Expanded tolerance for testing counter overflows
due to the loss of uniform control of the gloabl_ctrl register
Adding some pmu_version() return value checks can seamlessly support
Intel Arch PMU Version 1, while opening the door for AMD PMUs tests.
Signed-off-by: Like Xu <likexu@xxxxxxxxxxx>
---
x86/pmu.c | 64 +++++++++++++++++++++++++++++++++++++------------------
1 file changed, 43 insertions(+), 21 deletions(-)
diff --git a/x86/pmu.c b/x86/pmu.c
index 25fafbe..826472c 100644
--- a/x86/pmu.c
+++ b/x86/pmu.c
[...]
@@ -520,10 +544,13 @@ static void check_emulated_instr(void)
"instruction count");
report(brnch_cnt.count - brnch_start >= EXPECTED_BRNCH,
"branch count");
- // Additionally check that those counters overflowed properly.
- status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
- report(status & 1, "instruction counter overflow");
- report(status & 2, "branch counter overflow");
+
+ if (pmu_version() > 1) {
+ // Additionally check that those counters overflowed properly.
+ status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS);
+ report(status & 1, "instruction counter overflow");
+ report(status & 2, "branch counter overflow");
+ }
This should use status bit 1 for instructions and bit 0 for branches.
Yes, this misleading statement stems from
20cf914 ("x86/pmu: Test PMU virtualization on emulated instructions")
I will fix it as part of this patch set. Thanks.
report_prefix_pop();
}
[...]
- Sandipan
